Single-transistor floating body memory cells base upon charge storage effects in an insulated floating semiconductor body. The floating body is sandwiched between two source/drain regions, wherein the first source/drain region may be connected to a source line or a common source plate and a second source/drain region may be connected to a bit line. A gate electrode is configured to switch a current between the two source/drain regions by a select voltage applied to the gate electrode. By applying a suitable write signal to the gate electrode or to the gate electrode and the source line/common source plate, charge may be injected in or removed from the floating body in accordance to a voltage supplied to the bit line. By applying a suitable read signal to the gate electrode or to the gate electrode and the source line/common source plate, an output signal may be caused in the bit line, wherein the output signal depends on the amount and/or type of charge stored in the floating body region. Typically, the read signal differs from the write signal, for example with regard to the voltage amplitude.
A need exists for integrated circuits comprising a high density floating body memory cell array and simple peripheral circuitry for addressing the memory cells of a floating body memory cell array.